Showing posts with label Reading and Writing binary files in Systemverilog. Show all posts
Showing posts with label Reading and Writing binary files in Systemverilog. Show all posts

Saturday, February 5, 2022

Reading and Writing Binary files in Systemverilog

Reading a binary file in SystemVerilog might be required occasionally. I have tried to capture some basic information as a guide for someone starting out. 

Comments are embedded in the code: 


Similarly an example for writing a binary file