Binding in Systemverilog

Assertions are written both by design engineers and verification engineers depending on what is being checked and wherein the design hierarchy. If Assertions reside inside design modules which are going to be synthesized then these assertions which solely meant for checking/verification have to be enclosed inside compilation directives like ifdef so they can be hidden from Synthesis tools. As an alternative, Systemverilog provides bind feature which allows specific modules which contain all the assertions to be bound during elaboration. This feature essentially instantiates assertion module inside design module and all the assertions behave as if they reside inside the design. This enables engineers to keep verification code separate from design code.

Syntax:

bind <target RTL module> [:<name of the target instances>] <assertion module> <binding instance name> (<port list>);

where
[<name of target instance>] is optional. If nothing is specified, binding is done on all the target RTL module instances

<assertion module> is the module which contains all the assertion code.

<port list> is the port connections from target RTL module to assertion module.

Assertion module is like any other module. Keep below points in mind:

• Define all the inputs required for assertions as input ports.
• No outputs from assertion module as it is strictly not for driving anything into the design
• Input Port names can be name. If you decide to keep the same port names as the net name of target design module then you while binding .* would automap the connections. Connect by name if the input port name is different from the net in the target design module
• If any internal probes from instances below target design module are required for the assertion then same can be made as input to the assertion module and passed as an argument while making assign hierarchical probing at the target module. This should be avoided for any synthesizable block and usage is mostly intended for bmod assertions which requires internal probing

Ex:
Binding to all modules with name module_name:
bind module_name inst2_assert inst2a(.mode(mode_value),
                                                               .order(order)
                                                             );


Binding to the specific instance with name inst2 (Instance binding):
bind module_name:inst2 inst2_assert inst2a(.mode(mode_value),
                                                                       .order(order)
                                                                       );

Ex:

Enabling and Disabling Assertions

Many times, assertions need to be disabled based on the test or during the simulation. For example,   some assertions are not really valid before reset(not counting disable iff feature of assertion property) and you might want to switch off those assertions. Similarly, the case when there is mode transition you might want to switch off certain assertions till transition is complete and then re-enable.

There are different methods to enable and disable assertions. Below explanation summarizes it

1) Use of $assertoff and $asserton system Verilog tasks

$assertoff is used to switch off assertions. We can use this systemverilog task anywhere in the testbench like classes, modules etc including UVM tests, sequences, driver, initial block of a module.

Syntax:

$assertoff[("levels" [,"hierarchical path to instance of modules or assertions "];

Where

"levels" is an optional argument which specifies the hierarchy levels below the instance name(next optional argument)

"hierarchical path to an instance of modules or assertions"> is an optional argument indicating an instance of module or assertions to be turned off

Ex- let's say,  top is the name of the top level of the testbench in which design instance mydut is instantiated. Design instance has fsm_logic instance.

$assertoff(0,top);

Level 0 => All assertions in module top and below in the hierarchy to be turned off. This essentially switches off all the assertions inside the design as the module top is the top of the testbench including the ones inside mydut and fsm_logic

$assertoff(1,top.mydut);

Level 1 => only assertions in module instance mydut will be turned off while assertions in other instances will continue to fire.

$assertoff(2,top);

Level 2 => Assertions in instance top module and one level below top module(mydut is the only module instance inside top) will be turned off.
$assertoff with no arguments turns off all assertions in all modules.
You can switch of specific assertions inside the module if the assertion has name
Ex:
Dummy property will fail if it ever fires. It is coded to fire in the first rising clock.

Use $asserton similarly with the same syntax as $assertoff

Problem with this method of enabling or disabling
• It requires the hierarchical path to module or assertion and is very painful as we go up in integration.
• Nonreusable as the hierarchy might change anytime


2) Use of Verilog Attributes to create Assertion categories and switch on/off assertions based on vendor-specific nonstandard system tasks

Attributes were created in Verilog 2001 as a way to define and attach some characteristics for tool specific usage.

Ex: While inserting DFT Mux called VISA by specific visa tool, it inserts ports with tool attribute with tool specific number
Syntax:

(* [=] *)

Where [=] is the name assigned to attribute. This constant can be string or number or both.

Simulation Vendors like Synopsis VCS provide many nonstandard tasks which will enable us with the capability to disable or enable these tool-specific features. We can categorize assertions then use these nonstandard tasks to disable or enable assertions

Ex:

(* category = 6 *)
category_example:assert property(check_something);

I have used VCS tool for simulation and hence these examples are going to be specific to VCS while the same concept can be used elsewhere with the similar approach

VCS Specific Tasks:

   Stops all assertions associated with the specified category level (an unsigned integer from 0 to 2^24– 1):

$ova_category_stop([Category number]);

  Starts all assertions associated with the specified category:

$ova_category_start([Category number]):

Note that these tasks can be used anywhere including UVM sequences, test or driver etc

The category attribute, along with $ova_category_stop and $testplusargs arguments can be used enable or disable assertions.
lets rewrite the assertion in one of the design example above with added category:

(*category=1501*)
DUMMY_ASSERT : assert property (p_dummy) `uvm_info(""design_module"", "DUMMY", UVM_HIGH) else `uvm_error("design_module", $sformatf("p_dummy failed"))

Call below function before the simulation starts anywhere in _test_base or test

function void check4sva_argument();

    int sva_category;

    if($value$plusargs("sva_disable_category_number=%0d", sva_category))

    begin

        $ova_category_stop(sva_category);

        `uvm_info(get_type_name( ), $sformatf("Turning off SVA Category=%0d",sva_category), UVM_LOW)

    end

endfunction

Formalizing SVA Categories:

There are many DUTs which might want to take benefit of this feature and the same testbench might get integrated at SOC level for reuse purpose.  There is a quite a possibility of different testbenchs end up using the same category number for different assertions which might result in a clash and hence false pass. Therefore, Formalization of these categories is must.